历史上失败的存储技术比比皆是。但前英特尔CEO帕特·基辛格认为，佐治亚理工学院研究人员利用氧化物半导体开发的一种新兴存储技术，可能是这一规律的例外。
History is littered with the ruins of failed memory technologies. But former Intel CEO Pat Gelsinger believes an emerging memory tech developed by researchers at Georgia Tech using oxide semiconductors may be the exception to the rule.
“基本上，三十年来存储领域没有出现过重大创新形式——SRAM、DRAM和Flash是唯一广泛部署的存储类型，”基辛格告诉《The Register》。
"Essentially, we’ve had no major forms of innovation in memory for three decades – SRAM, DRAM, and Flash as the only memory types in broad deployment," Gelsinger told El Reg.
Nagare Labs的Z2RAM旨在改变这一现状，提供一种存储技术，其速度接近SRAM，密度则更接近DRAM，同时比HBM或LPDDR更容易制造。
Nagare Labs' Z2RAM aims to change that by delivering a memory tech that's nearly as fast as SRAM at a density much closer to that of DRAM, while also being easier to manufacture than HBM or LPDDR.
“基本上，他们将DRAM、SRAM和Flash的最佳特性结合在一个新器件中，该器件既像DRAM一样高密度，又像SRAM一样快速，还像Flash一样易于扩展，”基辛格表示。“虽然HBM有许多局限性（功耗、密度、海岸线带宽），但其密度与性能的结合是目前可用的最佳方案。这正是Z2RAM带来的价值，提供了更好的密度、速度和功耗表现。”
"Fundamentally, they are combining the best characteristics of DRAM, SRAM, and flash into a new device that is both dense like DRAM, fast like SRAM, and scalable like flash," Gelsinger said. "While HBM has many limitations (power, density, shoreline bandwidth) the combination of its density and performance is the best available today. This is exactly the value that Z2RAM brings, giving better density, speed and power."
这也解释了为什么投资方Playground Global——基辛格去年加入成为合伙人——正在帮助资助Nagare的开发工作。
This explains why investor Playground Global, where Gelsinger became a partner last year, is helping to bankroll Nagare's development efforts.
SRAM般的速度，DRAM般的密度由佐治亚理工学院教授Sumem Datta和Shimeng Yu创立的Nagare Labs，是多年来对铁电存储和电阻式RAM等下一代存储技术研究的结晶。
SRAM-like speed, DRAM-like density Founded by Georgia Institute of Technology professors Sumem Datta and Shimeng Yu, Nagare Labs is the culmination of years of research into next-generation memory technologies like ferroelectrics and resistive RAM.
该技术基于氧化物半导体构建，旨在利用3D混合键合技术直接集成到计算逻辑上。在这方面，Z2RAM将扮演类似于AMD 3D V-Cache SRAM堆叠技术的角色。
The technology is being built on oxide semiconductors and is designed to be integrated directly onto compute logic using 3D hybrid bonding technologies. In this respect, Z2RAM will fill a similar role to AMD's 3D V-Cache SRAM stacking tech.
如果你熟悉需要额外L3缓存的CPU，AMD利用先进封装将一块64MB的SRAM芯片键合在CPU小芯片的上方或下方，实际上将其SRAM容量增加了两倍。Z2RAM的概念类似，但其首代产品有望实现比SRAM高出5倍以上的位密度。
If you're familiar with CPUs requiring additional L3 cache, AMD uses advanced packaging to bond a 64MB SRAM tile either above or below its CPU chiplets, effectively tripling their SRAM capacity. Z2RAM is similar in concept, but promises bit density upwards of 5x that of SRAM in its first incarnation.
因此，如果您观察一块 64MB 的 SRAM 晶粒，Nagare 的 Z2RAM 晶粒可在相同空间内提供 320MB 的容量，且带宽与 SRAM 相当。虽然与搭载 HBM 的加速器相比，这听起来容量并不大——例如 Nvidia 的 Rubin 拥有 288GB 容量，AMD 的 MI455X 拥有 432GB 容量——但 Z2RAM 相较于基于 SRAM 的加速器（如 Nvidia 的 Groq LPU）实现了重大改进。
So if you were to look at a 64MB SRAM tile, Nagare's Z2RAM tiles would offer 320 MB of capacity in the same space, at bandwidth comparable to SRAM. While that may not sound like a lot of capacity compared to HBM-heavy accelerators like Nvidia's Rubin with its 288 GB capacity, or AMD's MI455X with its 432 GB, Z2RAM presents a major improvement over SRAM-based accelerators like Nvidia's Groq LPUs.
目前，Nvidia 的 Groq 3 LPU 每颗芯片约配备 500MB SRAM，因此需要数千颗加速器才能大规模服务前沿大语言模型（LLM）。Z2RAM 可将所需芯片数量减少 5 倍甚至更多。“随着 AI 需求的爆发，我们看到了对内存的非凡需求，因为 AI 是一种受内存限制的工作负载。在此背景下，人们对能够解决 AI 所带来的带宽和容量挑战的突破性技术表现出非凡的兴趣，且现在已有资金可用，”Gelsinger 告诉我们。
Today, Nvidia's Groq 3 LPUs feature about 500 MB of SRAM per chip, necessitating thousands of accelerators in order to serve frontier LLMs at scale. Z2RAM could cut the number of chips required by 5x or more. "With the explosion of AI demand, we’ve seen an extraordinary demand in memory as AI is a memory-limited workload. With that backdrop, there is extraordinary interest and now capital available for a breakthrough that solves the bandwidth and capacity challenges that AI is creating," Gelsinger told us.
看妈，没有电容Nagare 利用基于晶体管而非电容器的存储单元，实现了这一密度与带宽的壮举。“在速度方面，它将媲美 SRAM；但在功能上，它更像 DRAM，因为其存储机制的缘故，”联合创始人 Datta 告诉我们。“DRAM 是一晶体管一电容，一个无源物理电容。Z2RAM 实际上是两个晶体管，但……我们利用第二个晶体管的栅极电容来存储电荷。”
Look Ma, no capacitors Nagare achieves this density and bandwidth feat using memory cells based on transistors rather than capacitors. "In terms of speed, it's going to rival SRAM, but in terms of functionality, it is more like a DRAM because of the storage mechanism," cofounder Datta told us. "DRAM is one transistor, one capacitor, one passive physical capacitor. Z2RAM is actually two transistors, but ... we are using the gate capacitance of the second transistor to store the charge."
由于电荷存储在晶体管中，读取过程变为非破坏性，从而实现了优于 DRAM 的延迟。这是因为读取 DRAM 单元时，其电容器会被耗尽。“读取完成后，您必须将数据写回单元，”他解释道。全晶体管架构并非 Z2RAM 的唯一绝技，因为 Nagare 正在追求一种技术与工艺，将使其能够垂直堆叠这些存储单元。
Because that charge is stored in a transistor, reading it becomes non-destructive, which allows for better latency than you would get from DRAM. That's because when a DRAM cell is read from memory, its capacitor is drained. "After your reading is complete, you have to write back into the cell," he explained. The fully transistor-based architecture isn't Z2RAM's only party trick because Nagare is pursuing a technology and process which will allow it to stack these cells vertically.
虽然这听起来很像 HBM 或 LPDDR，但 Datta 表示，它实际上更类似于 NAND 闪存的层叠构建方式，这理论上意味着 Z2RAM 的制造成本应大幅降低，且更易于生产。前路漫漫完成首轮种子融资后，Nagare 现拥有 500 万美元用于进一步开发该技术。就半导体技术而言，这笔资金并不算多，但 Datta 也是第一个承认该初创公司的技术几乎还未走出实验室的人。
While that might sound a lot like HBM or LPDDR, Datta says it's actually more akin to how NAND is built up in layers, which in theory means that Z2RAM should be dramatically cheaper and easier to manufacture. A long road ahead With its first seed funding round behind it, Nagare now has $5 million to further the development of the tech. As semiconductor technologies go, this isn't a lot of money, but Datta is also the first to admit the startup's tech has barely left the lab.
“我们目前的状态实际上就是实验室原型，”他说。公司目前正在寻找研发晶圆厂合作伙伴，帮助其将生产规模扩大到大学洁净室之外，目标是在未来四年内推出可工作的 Z2RAM 存储芯片样品，并在未来十年内实现量产出货。Datta 表示，公司也愿意直接与芯片制造商合作，将 Z2RAM 集成到他们的设计中，类似于 AMD 与台积电合作开发 3D V-Cache 芯片的方式。
"Where we are is literally lab prototypes," he said. The company is currently looking for an R&D fab partner to help it scale production beyond the university clean room, with the goal of sampling working Z2RAM memory tiles within the next four years and a goal of production shipments within the next decade. Datta says the company is also open to working directly with chipmakers to integrate Z2RAM into their designs, similar to how AMD worked with TSMC on its 3D V-Cache tiles.
公司在集成方面也面临挑战。“目前我们没有任何标准来将这种新型存储器与加速器集成，”Yu 表示。“要释放这种大容量、高速存储器的优势，我们必须使用 3D 邦定技术，而目前对此尚无标准化。”
The company also faces challenges with regard to integration. "There's no standard that we have right now to integrate this new memory with the accelerator," Yu said. "To unleash the benefits of this high capacity, high-speed memory, we have to use 3D bonding, and right now there's no standardization for that."
他补充道：“AMD 当然拥有 V-Cache，但那是专有技术。”Yu 告诉我们，如果没有开放的行业标准，为了让 Z2RAM 得到广泛采用，Nagare 可能不得不自行设计接口，这绝非易事。
"AMD, of course, has the V-Cache, but it's a proprietary technology," he added. In order for Z2RAM to see wide adoption without an open industry standard, Yu tells us that Nagare may have to design an interface itself, which is no small task.
还有验证方面的担忧。Nagare 正在使用氧化物半导体，Datta 告诉我们，这种材料具有更好的热性能和辐射性能，但也容易产生原子空位。他解释道：“即使是‘单电子效应或少数电子效应也会导致晶体管的阈值电压发生微小变化，而这足以扰乱该存储单元。’”因此，人们正投入大量精力，致力于最大程度提高 Z2RAM 存储单元的可靠性。
There are also validation concerns. Nagare is working with oxide semiconductors, which Datta tells us benefit from better thermal and radiation performance, but are also prone to atomic vacancies. Even "single electron effects or few electron effects can cause the threshold voltage of the transistors to move just a wee amount, and that will be enough to actually upset that cell," he explained. Because of this, a lot of effort is going into maximizing the reliability of the Z2RAM memory cells.
“曾有那么多存储初创公司，但它们都没有成功，”达塔说。“你可能拥有最惊人的存储技术，但由于标准极其严苛，永远无法进入系统。”不过，达塔认为形势已经发生变化。动态变化和新协议的出现，再次为在存储领域大胆创新打开了大门。®
"There have been so many memory startups and they didn't succeed," Datta said. "You might have the most amazing memory technology, but you can never penetrate the system because of the stringent standards." However, Datta believes the landscape has changed. Changing dynamics and the emergence of new protocols have opened the door to being adventurous with memory again. ®