在预热其 256 核心 Epyc 处理器一年多之后，AMD 终于准备好谈论 Zen 核心的架构变革，这些变革不仅使高核心数成为可能，最终还将为其下一代用于台式机和移动 PC 的 Ryzen 处理器提供动力。在上周于拉斯维加斯举行的媒体发布会上，AMD 透露了其最新 Zen 核心的细节，承诺在各种 AI 和服务器工作负载上，每时钟周期指令数（IPC）平均提升 27%，并将加速频率提升至 4.1 至 5.3 GHz 范围。
After teasing its 256-core Epycs for more than a year, AMD is finally ready to talk about architectural changes to the Zen core that not only make it possible, but will eventually power its next generation of Ryzen processors in desktop and mobile PCs. During a press event in Las Vegas last week, AMD spilled the beans on its latest Zen cores, which promise an average 27 percent uplift in instructions per clock (IPC) across a variety of AI and server workloads, along with boosted clocks ranging from 4.1 to 5.3 GHz.
我们预计消费级芯片很快将达到更高频率，但 AMD 尚未准备好谈论 Ryzen 产品。CPU 性能取决于功耗、IPC 和频率三者，三方面均有提升，这些核心有望成为公司有史以来最大的代际飞跃之一。
We expect to see even higher frequencies on consumer chips before long, but AMD isn’t quite ready to talk about Ryzen just yet. CPU performance is a function of power, IPC, and clocks, and with gains across all three, the cores are shaping up to be one of the company’s biggest generational jumps ever.
双核心故事与以往的 Epyc 发布一样，Zen 6 并非单一核心。它分为两种版本：频率优化版（Zen 6）和密度优化版（Zen 6c）。这种拆分可追溯至 2023 年 AMD Bergamo（霄龙）Epyc 处理器的发布，该处理器在仅八个芯片小片中封装了 128 个紧凑型 Zen 4c 核心。该芯片的首秀因显而易见的原因引发了与 Intel 当时仍相对较新的能效核（E-cores）的比较。
A tale of two cores As in past Epyc launches, Zen 6 isn’t one core. It comes in two flavors: a frequency-optimized variant (Zen 6) and a density-optimized version (Zen 6c). This split dates back to the launch of AMD’s Bergamo Epycs in 2023, which packed 128 compact Zen 4c cores into just eight chiplets. The chip’s debut drew comparisons to Intel’s still relatively new Efficient (E-cores) for obvious reasons.
但从内部来看，AMD 的 Zen 4c 与 Intel 的做法截然不同。核心本身与 Zen 4 几乎相同；它只是用频率和每核心一点缓存换取了更紧密堆积的 CPU 晶圆。在 Bergamo 还是 Genoa（热那亚）上运行应用程序的唯一区别在于执行速度快慢。对于 Intel 的 P 核和 E 核则不能这么说，它们使用不同的指令集架构（ISA）。
But under the hood, AMD’s Zen 4c was nothing like what Intel was doing. The core itself was nearly identical to Zen 4; it simply traded clocks and a bit of cache per core for a more densely packed CPU die. The only difference between running an application on Bergamo or Genoa was how quickly it executed. The same could not be said of Intel’s P and E cores, which used different ISAs.
这一特性一直是 AMD 紧凑型核心架构的决定性特征和优势，延续至 Zen 5，使其能够推出多达 192 核心的 Turin（都灵）产品，而用户无需担心其应用程序运行在紧凑型核心还是标准核心上。就我们目前的理解而言，Zen 6c 在很大程度上延续了这一理念。
This remained a defining characteristic and advantage of AMD’s compact core architecture through Zen 5, which allowed it to ship Turin parts with up to 192 cores without users having to worry about whether their app was running on a compact core or not. With Zen 6c, at least as we understand it, this philosophy is largely unchanged.
Zen 6 和 Zen 6c 共享相同的 ISA，时钟频率是两者的主要区别。两个核心之间还存在其他微架构差异，旨在更有效地平衡 IPC（每时钟周期指令数）和时钟速度。从核心的框图来看，这一点并不明显。Zen 6 和 Zen 5 拥有非常相似的前端和后端。如果不是 AMD 声称 Zen 6 在云和 AI 工作负载上比 Zen 5 实现了 20% 到 31% 的 IPC 提升，我们会倾向于称该核心为迭代式更新。
Both Zen 6 and Zen 6c share the same ISA, with clock being the main differentiator. There are other micro-architectural differences between the two cores designed to balance IPC and clock speeds more effectively. Looking at the core’s block diagram, this isn’t immediately obvious. Zen 6 and Zen 5 share a very similar front and backend. We'd be tempted to call the core iterative if it weren't for the 20 to 31 percent IPC uplift for cloud and AI workloads that AMD claims over Zen 5.
这表明，就单核而言，一颗 4.1 GHz 的基于 Zen 6c 的 Venice Epyc 处理器，其性能应与一颗运行在 5 GHz 的基于 Zen 5 的 Turin Epyc 处理器持平。这是一个相当大的飞跃，但 AMD 在企业服务器和云工作负载上看到代际性能提升，并不意味着客户端侧会看到相同的增益。许多人会记得，游戏 PC 爱好者报告 Ryzen 9000 系列的性能增益约为 5%，从而导致了颇为不幸的“Zen 5 percent”（Zen 5%）这一说法。
This suggests that core for core, a 4.1 GHz Zen 6c-based Venice Epyc should deliver performance on par with a Zen 5-based Turin Epyc running at 5 GHz. That's a pretty sizable jump, but just because AMD is seeing generational performance uplift in enterprise server and cloud workloads doesn't mean we'll see the same gains on the client side. Many will recall the roughly 5 percent performance gains gaming PC enthusiasts reported with the Ryzen 9000-series, leading to the rather unfortunate turn of phrase "Zen 5 percent."
之所以发生这种情况，是因为当时的游戏引擎根本不是 CPU 瓶颈，因此更快的核心只能在有限程度上提高性能上限。即便如此，AMD 资深研究员、“Zen 之父”Mike Clark 告诉《El Reg》（The Register），PC 买家期望 Zen 6 带来的增益超过 6%。我们略过了许多底层架构优化，但据 Clark 称，最大的性能驱动因素之一是前端的改进。
That happened because game engines at the time simply weren't CPU-bottlenecked, and so faster cores could only raise the ceiling so much. Even so, AMD fellow and "Zen daddy" Mike Clark tells El Reg that PC buyers expect more than a 6 percent gain from Zen 6. We're glossing over a bunch of low-level architectural optimizations here, but according to Clark, one of the biggest drivers of performance was to the front end.
Zen 5 引入了双前端，这对简单工作负载效果很好，但在面对更动态的负载时却损失了大量性能。Clark 表示：“Zen 6 团队为那些具有双极性质的大规模工作负载做得非常出色。这在框图中不太直观，你很难从框图中看出。这有点微妙……但它是一个巨大的杠杆。”另一个贡献因素是乱序流水线采用了分布式调度器。
Zen 5 introduced a dual front end, which for simple workloads worked great, but lost a lot of steam when confronted with more dynamic loads. "The Zen 6 team did a really good job for those larger footprint workloads that have a bipolar nature," Clark said. "It's not something that comes through. You're not going to see it in a block diagram very well. It's sort of subtle... but it's a big lever." Another contributor was the move to a distributed scheduler in the out-of-order pipeline.
现代 CPU 核心最大的性能驱动因素之一在于：它们并不按接收顺序执行指令。相反，它们会对指令进行重新排序，以便让核心的后端执行单元持续获得指令流。这正是 Zen 6 与 Zen 6c 最大的差异所在。为弥补后者较低的时钟频率，AMD 为该核心的调度器配备了更深的队列，Clark 告诉我们，这有助于处理高延迟工作负载。
One of the biggest performance drivers in modern CPU cores is that they don't execute instructions in the order they receive them. Instead, they reorder the instructions so as to keep the core's backend execution units fed with a constant stream of instructions. This is where we see the biggest difference between Zen 6 and Zen 6c. To account for the slower clocks on the latter core, AMD gave the core's scheduler deeper queues, which Clark tells us helps with higher-latency workloads.
与此同时，据我们了解，Zen 6 较浅的队列使其能够在更低功耗下实现更高主频。最后，在后端方面，AMD 做出了若干细微调整，这对向量密集型工作负载（包括 AI）将产生重大影响。其中较为显著的一项是：每周期可执行四次 AVX2 或两次 AVX-512 加载操作。虽然这对 AVX-512 性能提升不大，但对于尚未更新以使用 AVX-512 的应用程序，核心现在能执行两倍的加载操作，这应能提升传统应用的吞吐量。
Meanwhile, from what we understand, Zen 6's shallower queue enables it to clock higher on less power. Finally, on the backend, AMD made several subtle changes which should have major implications for vector heavy workloads, including AI. One of the more significant was the ability to perform four AVX2 or two AVX-512 loads per cycle. While this doesn't improve AVX-512 performance much, for applications that haven't been updated to use it, the core is now able to perform twice as many loads, which should improve throughput for legacy applications.
这在 PC 端尤为实用，因为 Intel 完全不支持 AVX-512，导致 AVX2 成为大量软件的最低共同标准。这并非说 AVX-512 这一代未获青睐。对于在 CPU 上运行 AI 工作负载的用户，Zen 6 现原生支持 FP16 数据类型。此前虽支持 FP16，但需将数据填充至 FP32，导致低精度在性能上优势不大。而在 Zen 6 中这种情况已不复存在。
This should come in handy, particularly on PCs, where Intel's outright lack of AVX-512 support has made AVX2 the lowest common denominator for a lot of software. That's not to say AVX-512 didn't get some love this generation. For those running AI workloads on CPUs, Zen 6 now natively supports FP16 datatypes. Previously FP16 was supported, but required padding the data to FP32, which meant the lower precision didn't buy much in terms of performance. That's no longer the case in Zen 6.
谈到 AI 加速，Clark 指出 Zen 6 将 VNNI-INT8 通道从两个增加到四个，对于支持该特性的工作负载，吞吐量应可有效翻倍。喂饱“野兽” 虽不严格属于核心部分，但 AMD 的 Zen 6 处理器还解决了其频率优化核心与密度优化核心相关的最大不对称问题之一。
And while we're on the topic of AI acceleration, Clark notes that Zen 6 doubled the VNNI-INT8 pipes from two to four, and should effectively double throughput for workloads that support it. Feeding the beast While not strictly part of the core, AMD's Zen 6 processors also address one of the biggest asymmetries associated with its frequency and density optimized cores.
回顾博格（Bergamo）处理器，选择密度优化型 Epyc 不仅以降低主频为代价，还牺牲了缓存。每个 Zen 4c 或 Zen 5c 芯片组包含的核心数量翻倍，但 L3 缓存容量保持不变。随着 Zen 6 和 Zen 6c 的推出，虽然可能仍需在主频上做出让步，但每核心缓存现已固定为 4 MB。正如我们在 9 月的威尼斯（Venice）架构深度解析中所讨论的，处理器的八个 CPU 芯片分别包含 12 核或 32 核，对应的 L3 缓存容量分别为 48 MB 和 128 MB。
Going back to Bergamo, opting for a density-optimized Epyc didn't just come at the expense of clocks, but cache too. Each Zen 4c or Zen 5c chiplet contained twice as many cores, but the same amount of L3 cache. With Zen 6 and Zen 6c, you may be giving up some clocks, but cache per core is now a constant 4 MB. As we discussed in a Venice deep dive back in September, each of the processor's eight CPU dies contain 12 or 32 cores and 48 and 128 MB respectively.
其优势在于，用户在针对 AMD Epyc 处理器优化软件栈时，无需担心不同的指令集架构（ISA）或缓存层级。英特尔至强（Xeon）处理器则无法做到这一点。正如我们早前所暗示的，芯片巨头（Chipzilla，指英特尔）的性能核（P-core）和能效核（E-core）采用不同的微架构、指令集架构、缓存层级、主频，甚至核心簇组织方式也不同。
The benefit here is that users don't have to worry about different ISAs or cache hierarchies when optimizing their software stacks against AMD's Epyc processors. The same cannot be said of Intel's Xeon processors. As we alluded to earlier, Chipzilla's performance and efficiency cores use different micro-architectures, ISAs, cache hierarchies, clocks, and even cluster their cores differently.
如果工作负载利用了宽向量寄存器（如 AVX-512）或加速器（如 AMX），这会带来实实在在的麻烦：这些指令在英特尔 P 核上运行良好，却根本无法在 E 核上运行。加上对 SMT（超线程）的支持——英特尔目前已放弃该技术——这些因素可能助力“禅之殿堂”（House of Zen，指 AMD）从老对手手中抢夺更多市场份额。®
This can pose real headaches if you have workloads that take advantage of fat vector registers like AVX-512, or accelerators like AMX, which will work just fine on Intel's P-cores but won't even run on their E-cores. This, along with support for SMT (Hyperthreading), which Intel has dropped for now, could help the House of Zen vacuum up even more market share from its long-time rival. ®