AMD 的大缓存 Epyc X 系列芯片正式宣布回归。基于我们在 9 月份关注的“禅之屋”针对频率优化的 SKU，其面向 HPC（高性能计算）优化的 Venice-X 部件将提供多达 96 个核心，并采用公司的 3D V-Cache 芯片堆叠技术，将 L3 缓存密度提高两倍，达到 1GB 以上。但在你对另一款大缓存 Epyc 过于兴奋之前，实际发货还需要一段时间。AMD 预计 Venice-X 将于 2027 年下半年开始陆续推出。
AMD's cache-packed Epyc X chips are officially making a comeback. Based on the House of Zen's frequency-optimized SKUs we looked at back in September, its HPC-optimized Venice-X parts will offer up to 96 cores and use the company's 3D V-Cache chip stack tech to triple the L3 cache density to more than a gigabyte. But before you get too excited about another cache-packed Epyc, it'll be a little while before they actually ship. AMD expects the Venice-X to begin trickling out in the second half of 2027.
这些芯片在今年早些时候的 CES 上首次亮相，主要面向对延迟敏感的技术和科学计算工作负载，如计算流体动力学和电子设计自动化（EDA）。AMD 本身严重依赖其 X 系列 Epyc 处理 EDA 工作负载，如功能验证测试，该测试用于模拟硅片，以确保其按预期运行。据 AMD 资深研究员 Phil Steinke 介绍，通过在缓存中保留更多模型数据，CPU 核心不需要等待太长时间让数据在系统内存中进出。
First teased at CES earlier this year, the chips are primarily aimed at latency-sensitive technical and scientific computing workloads like computational fluid dynamics and electronic design automation (EDA). AMD itself relies heavily on its X-series Epycs for EDA workloads like functional verification testing, which is used to simulate silicon in order to ensure it behaves as it's intended to. According to AMD Fellow Phil Steinke, by keeping more of the model in cache, the CPU cores don't have to wait as long for data to move in and out of system memory.
通常情况下，增加 L3 容量需要更大的芯粒，这会导致良率降低，但过去四年 AMD 并非采用这种方式。相反，它利用先进封装技术，为现有的 CPU 芯粒加了一个小型的 SRAM “背包”。这项技术已历经几代产品，最早于 2022 年在 Ryzen 7 5800X3D 上首次亮相。那款消费级桌面芯片在一个 8 核芯粒顶部堆叠了一块 64MB 的 SRAM 晶圆，将 L3 容量提升至 96MB。
Normally, boosting L3 capacity would have required larger chiplets with lower yields, but that's not how AMD has gone about it for the past four years. Instead, it used advanced packaging to give its existing CPU dies a little SRAM backpack. This tech has been around for several generations now, having first debuted in the Ryzen 7 5800X3D back in 2022. That consumer desktop chip stacked a 64 MB SRAM tile on top of an 8-core chiplet, boosting L3 capacity to 96 MB.
额外的缓存使该芯片成为当时最强劲的游戏 CPU 之一。同年晚些时候，AMD 将同一技术引入其米兰架构的 Epyc 处理器，随着公司扩展产品组合以应对更广泛的工作负载。额外缓存广受欢迎，足以证明推出第二代 X 系列 Epyc 的合理性，后者于 2023 年发布。但随后就没有下文了。当 AMD 在 2024 年底发布第五代 Epyc 时，路线图上没有 Turin-X。
The extra cache made the chip one of the most potent gaming CPUs of the time. Later that year, AMD brought the same technology to its Milan generation of Epycs as the company expanded its portfolio to address a wider range of workloads. The extra cache was popular enough to justify a second generation of X-series Epycs, which launched in 2023. But then, nothing. When AMD unveiled its 5th-gen Epycs in late 2024, there was no Turin-X on the roadmap.
据AMD计算与企业AI产品业务负责人Madhu Rangarajan表示，这是有意为之。“我们不是每一代都推出X系列产品……企业HPC（高性能计算）市场的节奏往往稍慢一些，这决定了我们的产品节奏。”
According to Madhu Rangarajan, who runs AMD's compute and enterprise AI products biz, this was intentional. "We are not doing the X every generation.... The enterprise HPC kind of market tends to have a cadence that's a little bit slower, so that's what drives our cadence."
Venice-X标志着AMD X系列芯片的回归，总体而言，该处理器在很大程度上延续了前代产品的配方。该芯片最多包含八个CPU小芯片，现在每个小芯片都通过先进封装技术与一块96 MB的SRAM小芯片键合，每个小芯片的L3缓存总计144 MB，每个插槽总计1,152 MB，这与其取代的Genoa-X部件相同。但虽然核心数量和缓存容量没有增加，时钟频率却大幅提升，Venice达到5.3 GHz，而Genoa-X仅为3.7 GHz。
Venice-X marks the return of AMD's X-chips, and for the most part, the processor largely follows the same recipe as its predecessors. Each of the chip's up to eight CPU dies is now bonded to a 96 MB SRAM tile using advanced packaging, for a total of 144 MB of L3 per chiplet or 1,152 MB per socket, which you might have noticed is the same as in the Genoa-X parts they replace. But while core count and cache capacity haven't increased, clock speeds certainly have, with Venice now hitting 5.3 GHz compared to Genoa-X at just 3.7 GHz.
Rangarajan告诉《The Register》：“在Milan和Genoa时期，存在一种取舍。你必须在高频产品和带有3D V-Cache的产品之间二选一。HPC两者都需要。”将SRAM小芯片集成在计算小芯片顶部的堆叠方法需要这种妥协。将SRAM堆叠在计算小芯片顶部虽然增加了L3缓存，但也锁住了热量，从而限制了加速频率。因此，在Zen 5架构中，AMD将SRAM小芯片从堆叠顶部移到了底部。随着SRAM小芯片不再充当“隔热毯”，芯片能够以更高的温度和频率运行更长时间。
"In Milan and Genoa, there was one trade-off. You either had to choose something that was high frequency or you chose something with 3D V-Cache." HPC likes both, Rangarajan told El Reg. The method for integrating the SRAM tile required this kind of compromise. Stacking SRAM on top of the compute chiplets boosted L3 caches, but also trapped heat, which limited boost clocks. So, for the Zen 5 generation, AMD moved the SRAM tile from the top of the stack to the bottom. With the SRAM tile no longer acting as a blanket, the chips could run hotter and faster for longer.
但虽然游戏玩家在AMD的Ryzen 9000处理器上享受到了更高的频率和更大的缓存，直到现在随着Venice-X的推出，这些改进才进入Epyc产品线。由于客户不再需要在大缓存和高频率之间做选择，Rangarajan认为该芯片可能会获得更广泛的采用。“我认为它最终在HPC领域的规模将比前几代大得多，因为那时我们不得不做那种取舍。”
But while gamers enjoyed the higher clocks and bigger caches on AMD's Ryzen 9000 processors, only now with Venice-X are those improvements making their way into Epyc. Because customers no longer have to choose between big caches and fast clocks, Rangarajan believes the chip may see wider adoption. "I think it's going to end up being much bigger in HPC than the previous generations where we had to make that tradeoff."
有趣的是，如果频率不是如此高的优先级，Venice-X最初可能根本不需要3D堆叠SRAM。
Curiously, if frequency weren't such a high priority, Venice-X may not have needed 3D stacked SRAM in the first place.
正如我们今年早些时候报道过的，AMD 配置最高的 Venice 处理器拥有 256 个核心和 1024MB 的 L3 缓存。AMD 本可以直接屏蔽掉其中 160 个核心，从而实现类似的每核心缓存比例。事实上，AMD 在 Turin 这一代就做过类似的事情：对于 Epyc 9175F，AMD 基本上是拿了一款 128 核的产品，屏蔽掉了其中 112 个核心。
As we reported earlier this year, AMD's top-specced Venice CPUs boast 256 cores and 1,024 MB of L3 cache. AMD could have just fused off 160 of the cores and achieved a similar cache-per-core ratio. In fact, AMD did something like this for the Turin generation: For the Epyc 9175F, AMD essentially took a 128-core part and fused off 112 of the cores.
剩下的是拥有 512MB 末级缓存的 16 核产品。兰加拉詹说：“你可以对 Venice 这么做，但那样就无法获得其中的频率优势。Fmax 将是 4.1GHz，而不是 5.3GHz。”他补充说：“Venice X 真的改变了游戏规则。这是我们首次能在最高频率的产品中配备更大的 L3 缓存。”
What was left was a 16-core part with 512 MB of last-level cache. "You could do that [with Venice], but then you don't get the frequency part of it. The Fmax would be at 4.1 gigahertz and not 5.3 GHz," Rangarajan said. "Venice X really changes the game," he added. "For the first time, you can get the larger L3 in our highest frequency part." ®